Sky130 Magic- Comparators Layout Design

I already have complete Xschem schematics for three CMOS comparators—StrongARM, Double-Tail, and Triple-Tail—targeting the SkyWater 130 nm PDK. What I now need is the full-custom layout of each design in Magic, brought to a state where it meets the following requirements: * DRC-clean according to the standard Sky130 design rules * LVS-clean against the existing Xschem netlists * Power consumption, propagation delay, and input-referred offset should all be considered and optimized as much as reasonably possible during the layout design. Key Design Objectives There are three main performance criteria that are particularly important for this design: 1. Power consumption 2. Propagation delay 3. Input-referred offset These three parameters should be considered together throughout the layout process, and the impact of layout decisions on each parameter should be evaluated. The goal is to achieve the best possible balance between power consumption, speed, and offset performance, rather than prioritizing one parameter over the others. Particular attention should be paid to how layout decisions such as transistor placement, device matching, routing, and parasitic capacitance/resistance affect these three performance criteria. Scope of Work * Translate each existing Xschem schematic into an efficient full-custom Magic layout, following Sky130 layer conventions and design rules. * Optimize transistor placement and geometry where appropriate, without changing the intended circuit topology or functionality. * Use shielding, minimal metal jumps, and balanced differential routing where beneficial to reduce parasitic effects and minimize asymmetry in differential signal paths. * Pay particular attention to matching-critical transistors and differential signal paths. * Run DRC and LVS verification and provide the corresponding results. * Provide extracted netlists and parasitic extraction results so that the designs can be re-simulated in Ngspice with post-layout parasitics. * Evaluate layout-related trade-offs and their impact on power consumption, propagation delay, and input-referred offset. Deliverables * Three separate Magic layout files (.mag), one for each comparator * A merged GDSII file containing all three layouts * DRC and LVS reports demonstrating zero errors * Extracted netlists including C-parasitics for post-layout simulation and back-annotation * A short Markdown document describing the key layout considerations and design decisions, including transistor placement, device matching, routing strategy, shielding, parasitic reduction techniques, and other important layout considerations * A short Markdown note describing the major design trade-offs made with respect to power consumption, propagation delay, and input-referred offset Project Tracking and Collaboration The project can be tracked and managed through GitHub. Layout files, verification reports, extracted netlists, documentation, and subsequent revisions can be committed to the repository so that the development progress and changes can be tracked throughout the project. Intermediate stages and checkpoints can also be documented through GitHub commits and/or issues. This will allow the progress of each comparator to be tracked and reviewed independently throughout the layout, DRC, LVS, and post-layout extraction stages. Review and Checkpoints The standard Sky130 design rules are sufficient; no proprietary constraints are involved. The turnaround time and intermediate checkpoints are flexible, but the project should be completed and delivered as soon as reasonably possible. However, once each layout reaches a DRC-clean state, I would like to review the layout before proceeding with the final LVS verification, parasitic extraction, and final optimization/polishing stages.