KiCad fix + JLCPCB fab ownership — 0-10V - PWM PCB (showstoppers + DFM) -- 2

Need a strong **KiCad + JLCPCB** freelancer to **fully review and fix** my 4-layer Illuminator Hub, then **own upload → SMT map → placement check → production-ready quote** on **my JLCPCB account** (I approve payment). Project ZIP attached. Fixed scope, fast delivery — no open-ended redesign. **Board:** 8ch 0–10V hub (ESP32, W5500 + MagJack, DAC7678, OPA4197, CP2102N, USB-C, 24V in, LMR51430, TPS2116). Target: **JLCPCB PCB + SMT / LCSC**. ### Hard constraints - **Do not change PCB outline size or mounting-hole X/Y/drill** without written OK. You may change hole **netting** (e.g. isolate from digital GND). - THT **J1–J10, J11, J4** = hand-solder / DNP unless I say otherwise. - Minimal layout churn; LCSC parts. - **No paid JLCPCB order** without my explicit OK. ### Verification & quality bar (mandatory) I independently re-check schematic + PCB fitness in **three different AI/analysis environments** after each delivery. Work carefully and close issues **for real**. If the same class of defect reappears on the next check, I treat the revision as incomplete and require a **free rework** round. ### Source of truth **Every fix must be updated in the KiCad design files** (`.kicad_sch`, `.kicad_pcb`, symbols/footprints as needed) **and** in Gerber / BOM / CPL. **I do not accept** chat-only, PDF-only, or screenshot-only “fixes.” Unsynced schPCB or stale production files = **reject**. ### LED BOM (mandatory) - **LED1** (status RGB): [www.lcsc.com/product-detail](https://www.lcsc.com/product-detail/C965840.html) — **not Würth**. Correct footprint, pinout, wiring. - **All other LEDs:** [www.lcsc.com/product-detail](https://www.lcsc.com/product-detail/C52675991.html) — symbol, footprint, polarity, LCSC on every designator. ### Scope 1. Full sch + PCB review (electrical, SI, layout/DFM). 2. Fix **all** items below + any equal-severity bugs. 3. Gerbers + **full LCSC BOM** + **CPL**; ERC/DRC clean or documented waivers. 4. Upload to my JLCPCB; match SMT; validate pin-1/rotation; leave cart ready for my pay. 5. Change log tied 1:1 to file diffs. --- ## SHOWSTOPPERS (must fix — board will not work) **1. UART RX/TX not crossed (U8 CP2102N ESP32)** Today TXTX and RXRX (`/URAT_TX` / `/URAT_RX`). Fix: **CP2102N TXD → ESP32 RXD0**, **CP2102N RXD → ESP32 TXD0**. **2. DAC7678 I2C levels** U1 on **+5V AVDD** → VIH(min)≈**3.5V**; ESP32 + pull-ups at **3.3V**. Fix: **3.3V–5V I2C level shifter** (PCA9306 / BSS138) **or** power DAC at **3.3V** and revise op-amp gains if needed. **3. W5500 missing PHY terminations** Add WIZnet-style **4× 49.9Ω 1%** to 3.3V / center taps + center-tap decoupling. MagJack Bob Smith ≠ PHY termination. **4. Y1 25 MHz crystal** Add **XI/XO load caps** (~**18–22 pF** to GND). **5. ESP32 EN RC missing** **10k** to 3.3V + **1µF** to GND on EN. Keep SW1 / auto-program intact. **6. USB-only power / MUX** TPS2116 `/3.3V_Out` feeds only CP2102N; ESP32 on 24V-derived +3.3V → USB alone leaves ESP32 dead. Feed ESP32 (and needed logic) from MUX out or unify 3.3V for USB-only flash/test. **Also showstoppers if still present** - **IO12 strapping:** status LED red must **not** use IO12 — move to non-strapping GPIO. - **ESP32 Pin15 GND:** remove `no_connect`; tie to GND. - **Green LED `"G"` floating** — connect to a real GPIO. - **LED1** → **C965840** correct pinout (no Würth). - **D10** TVS: **≥28–30V** standoff (e.g. SMAJ28A / SMBJ28A), not PTVS22. - **P-MOS reverse polarity:** |VGS|max ±20V — **12–15V GS Zener** + proper gate divider/series R. - **TPS2116 PR1:** proper divider to 1.0V ref (not pull-up alone). - **CP2102N Pin8 VBUS:** **22.1k / 47.5k** divider. - **USB D+/D− ESD:** USBLC6-2SC6 or TPD2E001 (or equal). - **0–10V:** current-limit must not destroy op-amp FB; **47–100Ω R-iso** outside FB; **DAC→op-amp RC** (e.g. 1k+10nF). - **Ethernet chassis:** shield not hard-tied to digital GND — **1–2nF 2–3kV + ~1MΩ**; map MagJack shield pads correctly. - **Solder mask clearance** ~**0.05mm**; fine-pitch dams. - **Mounting holes:** don’t hard-stitch to digital GND (keep positions). ## SECONDARY (fix with showstoppers) 7. **W5500 PMODE[2:0] = 111** (all pulled high) for full auto-neg. 8. **IO0** external **10k** to 3.3V. 9. **0–10V shunt 47Ω** (~13.8mA) — revise toward **10–22Ω** if multi-ballast (ask if unsure). 10. Cleanup: CPL; full LCSC BOM; SW1/SW2 → `SW_Push`; `PWR_FLAG` on `/VBUS`; FID1–4; delete orphan EN-area wire. ### Leave unless broken Stackup + ESP32 antenna keepout; geometry vs JLCPCB limits; USB-C CC 5.1k; buck FB/bootstrap (aside from power-arch fix); auto-reset topology (aside from EN RC / UART cross / VBUS). ### Deliverables 1. Fixed KiCad project (sch + PCB + libs updated) 2. `production/`: Gerber ZIP + LCSC BOM + CPL matching the same revision 3. Project on **my JLCPCB** with SMT matched + placement validated (screenshots) 4. Quote/cart ready for **my** payment 5. Change log + ERC/DRC summary mapping each fix to designator/net **Skills:** KiCad, ESP32, Ethernet/W5500, analog, power, JLCPCB SMT, DFM.