AXI Stream Software Interface Integration

I am in the middle of a UCIE-based design and have reached the point where the AXI-Stream path must come alive. The remaining work is all about implementation: I already have the HDL side mapped out, but the stream interface still needs a clean, well-structured software layer so the rest of the system can push and pull data reliably. Here is what I need from you: • Translate the AXI-Stream handshake, data-movement rules, and side-band signals into a robust software abstraction that exposes simple, non-blocking read/write calls. • Supply concise, well-commented code (C/C++ or Rust—open to your recommendation) that can run on bare-metal or slot neatly into a lightweight RTOS. • Provide a minimal test application that shows packet construction, transfer, and verification against expected results so I can drop it straight into my existing simulation or hardware test bench. • Document the API and any configuration registers you touch so future developers can extend the driver without guesswork. Acceptance criteria 1. Clean compile with ‑Wall and no warnings. 2. Driver sustains full line-rate in a loop-back test using a 256-byte payload for 1 M packets without loss or mis-ordering. 3. All public functions are unit-tested; coverage report included. If you have recent experience binding AXI-Stream to software—especially in chiplet or multi-die contexts—let’s talk, and we can push this interface over the finish line.