Senior ASIC Design Engineer - Synthesis & Timing

Bitdeer Technologies Group is seeking an experienced IC Design Engineer in Singapore to drive synthesis, timing closure, and power optimization for ASIC designs. You will work closely with physical design teams on floorplanning, place & route, and timing bottlenecks, while applying low-power techniques and multi-clock domain awareness. Proficiency in Verilog/SystemVerilog and industry-standard EDA tools is required, with exposure to NoC/interconnect architectures. J-18808-Ljbffr