FPGA Hardware Engineer for PCIe Configuration

I am seeking an experienced FPGA hardware engineer to develop a custom 1:1 emulated PCIe core configuration for an Artix-7 device (35T/75T architecture). The objective of this project is hardware-level device emulation for system driver compatibility testing. The firmware must accurately replicate a targeted legitimate PCIe device configuration space so that the host operating system properly maps the hardware and initializes the standard manufacturer driver environment. Technical Requirements: • Base Framework: Custom implementation utilizing standard PCIe endpoint IP cores (or open-source PCIe protocol analysis frameworks). • Configuration Space Mapping: Precise configuration of Vendor ID (VID), Device ID (DID), Subsystem Vendor ID (SVID), Subsystem ID (SSID), Class Codes, and Device Serial Number (DSN). • Low-Level PCIe Mechanics: Proper mapping of BAR (Base Address Register) spaces, correct Transaction Layer Packet (TLP) handling, and implementation of standard MSI/MSI-X interrupt handling. • Performance: Stable, low-latency Direct Memory Access (DMA) transactions across the PCIe bus. Deliverables Required: 1. Complete Xilinx Vivado Project Source Files (including all .v/.vhd source files, .xdc constraints, and the .xpr project file). 2. Compiled bitstream configuration file (.bin / .bit). 3. Raw 'vivado.log' file from the compilation process to confirm a fresh and validated build timeline. Important Note: I do not require installation or flashing guides. I will require a minor configuration parameter change prior to final milestone release to verify full ownership and compilation capabilities of the provided source files. Please state your direct experience with Xilinx Vivado and PCIe configuration editing in your response.