Cost-Reduced LoRa Sensor PCB Redesign

SCOPE - 75 components, 47 nets, 240 connections. Single PCB, 4-layer (2 signal + solid GND + power), all SMD, one-sided placement preferred for JLCPCB assembly cost. - Board outline: > mm, 4x M3 mounting holes, connectors on specified edges. - Blocks: CN3163 solar Li-ion charger / DW01A+8205A cell protection / INA219 with 0R1 1206 shunt / TPS63802 buck-boost to 3V3 / two AO3401A gated rails / USB-C 2.0 with USBLC6 ESD / RYLR998 LoRa module / TTP223 capacitive touch pad / JST sensor headers. LAYOUT CONSTRAINTS (non-negotiable, these are why the job needs a real engineer) 1. TPS63802: inductor + input/output caps in the tightest possible loop, switch node copper minimised, solid ground return directly beneath. 2. The GPIO0 ADC divider (220k/68k) and the IPEX antenna line must be kept away from that switch node. 3. INA219 to the 0R1 shunt must be a true Kelvin/4-wire sense off the pad inner edges. 4. ESP32-C3-MINI-1U: antenna end overhangs the board edge, keepout on all layers, all 22 GND pads stitched to the pour. 5. USB D+/D- as a matched differential pair; USBLC6 within 5 mm of the connector, in series with the pair (not stubbed). 6. Touch IC within ~10 mm of its copper pad; thin, isolated trace. 7. Board must measure > before posting — nobody can bid honestly without the outline. Your locked TX form factor is a 110 × 80 × 35 mm enclosure around a 99 × 69 mm panel, so ~95 × 65 mm with the USB-C and JST edges called out is the sane default.