发布于 2026年10月17日 · 我们于 2026年11月09日 确认该职位仍然有效
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The ByteDance Silicon Platform Team is the core R&D middleware group for chip development, covering the full design flow from architecture to tape-out and mass production. You will design and optimize RTL/architectures, perform timing signoff, and implement low-power techniques in a collaborative environment across frontend and backend teams. We value strong Verilog/SystemVerilog skills, RTL-to-GDSII expertise, and proficiency with leading EDA tools for efficient power-optimized solutions in J-…