发布于 2026年9月07日 · 我们于 2026年10月02日 确认该职位仍然有效
这是您的公司吗？8 to 10 yrs of experience in DFT architecture, scan Insertion, compression at core level and SoC level. Experience in ATPG pattern generation, coverage analysis Experience with timing and no-timing simulations Experience in Memory-BIST Have understanding of SSN architecture, clock architecture, OCC
