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Senior Analog Layout Engineer

LeadSoc Technologies Pvt Ltd

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placeIndia home_work现场 labelScientific & QA Jobs public聚合职位 · IN

event发布于 2026年9月02日 · verified我们于 2026年10月03日 确认该职位仍然有效

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职位介绍

3 years of hands-on experience in Analog/Custom Layout . Strong experience in lower/advanced technology nodes . Experience in any of the following nodes is preferred: 16nm / 12nm / 7nm / 5nm / 3nm . Strong hands-on experience with Cadence Virtuoso / Virtuoso XL . Good knowledge of Calibre DRC/LVS or equivalent physical verification tools. Strong understanding of: Analog layout techniques Device matching Parasitics LDE EM/IR DFM ESD and latch-up Ability to read and understand analog schematics. …

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