Senior PCIe IP Design Engineer (Verilog RTL)

Bitdeer Development Pte. Ltd. in Singapore is seeking an experienced PCIe IP Design Engineer to develop and implement Verilog RTL for PCIe IP blocks and support verification closure.

The role

involves ensuring functional coverage and collaborating closely with verification and software teams to deliver robust, high-quality IP solutions.

Responsibilities

include supporting pre-silicon and post-silicon debugging, contributing to design verification, and assisting software development. J-18808-Ljb…