Published on Oct 03, 2026 · We confirmed on Oct 19, 2026 that it's still live
Is this your business?SGD 1.080 – SGD 1.560 / year
Bitdeer Development Pte. Ltd. in Singapore is seeking an experienced PCIe IP Design Engineer to develop and implement Verilog RTL for PCIe IP blocks and support verification closure.
involves ensuring functional coverage and collaborating closely with verification and software teams to deliver robust, high-quality IP solutions.
include supporting pre-silicon and post-silicon debugging, contributing to design verification, and assisting software development. J-18808-Ljb…
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